1. Field of the Invention
The subject matter of the present invention pertains to a computer system, and, more particularly, to a failure detection apparatus in said computer system for detecting the existence of a failure in a gating line thereby detecting the resultant transmission of erroneous data from one circuit module to another via a plurality of interface lines.
2. Description of the Prior Art
Adjacent integrated circuit modules are connected together by a multitude of interface lines. Data is transmitted from one circuit module to another via said interface lines. The data is subdivided into a plurality of bytes. Each byte of the data is transmitted from the one circuit module by a gating circuit, the gating circuit transmitting the data byte in response to a gating pulse. The gating circuit is connected to a latch circuit via a gate line. If the gate line is open or short circuited, or if some other abnormal circuit condition affects said gate line, the bytes of data will not be transmitted from the one circuit module to the other via the gating circuit accurately. As a result, another, adjacent circuit module will receive erroneous data for further processing of said data. Therefore, a failure detection apparatus is needed for detecting the existence of a failure, or other abnormal circuit condition, in the gate line in order to detect the existence of erroneous data and to prevent the transmission of further erroneous data.
In the prior art, in order to detect the presence of defective interface lines, including the gate line, redundant, duplex interface lines were provided for each interface line. If the interface line and its corresponding redundant duplex line were operational, an error signal was not generated. However, when the interface line failed, if the redundant duplex line was operational, an error signal was generated indicative of the presence of the defective interface line. However, the subsequent technological advance of integrated circuit technology reduced the size of integrated circuit chips and therefore reduced the number of input/output (I/0) pins on said chips. The interface lines are connected to said chips via said pins. Since the number of I/0 pins were reduced, the number of available interface lines were also reduced. As a result of the reduction in the number of interface lines, it was no longer feasible to utilize redundant, duplex lines to ensure the detection of defective interface lines. Another, alternative method of detecting the existence of a failing interface line, or a failing gate line was needed.
One alternative method utilized by the prior art is the so-called parity checking scheme. Each of the data bytes of said data include a parity bit. A convention is utilized wherein the parity bit of each data byte is selected in order to maintain, for example, an odd number of binary 1 bits in each transmitted byte of data. If a data byte was transmitted with an even number of binary 1 bits, the byte of data was transmitted erroneously.
However, this method cannot detect the existence of the failing gate line. Data should be transmitted such that odd and even data bytes are transmitted alternately, that is, in an "odd-even-odd . . . " sequence. If a gate line fails, the odd and even data bytes may be transmitted in an erroneous sequence, that is, in an "even-even" or in an "odd-odd" sequence. The above-mentioned method cannot check for data transmitted in an erroneous sequence.
One prior art publication, namely, IBM technical disclosure bulletin Vol. 18, No. 7, December 1975, page 2043, discloses a different type of parity checking scheme. In this scheme, alternate good and bad parity is forced through a parity checking circuit for the purpose of validating the operation of said circuit. This scheme is not set forth in an environment similar to the environment of the present invention, wherein a plurality of interface lines interconnect a plurality of miniature integrated circuits. In addition, this scheme fails to recognize the problems encountered in this environment, namely, the numerous failures which exist with respect to the interface lines and the gate lines which interconnect the miniature integrated circuits and the resultant transmission of erroneous data therebetween, especially with regard to the limited number of I/0 pins on said integrated circuits, the limited number of interface lines extending between adjacent ones of said integrated circuits, and the resultant difficulty of detecting said failures and the resultant transmission of erroneous data without utilizing additional redundant, duplex interface lines to ensure the accuracy of transmitted data.